1. Field of the Invention
The present invention relates to a CMOS pulse delay circuit which is used widely in a digital CMOS integrated circuit, and more particularly to the CMOS pulse delay circuit which may be suitable to a high-speed clock generator and a clock generating circuit to which the CMOS pulse delay circuit applies.
2. Description of the Related Art
The inventors of the present application know a pulse delay circuit which is arranged to have a MOS capacitor connected to an output of a CMOS inverter at the first stage. Then, the description will be oriented to the operating principle of the known pulse delay circuit as referring to FIG. 1.
As shown in FIG. 1, the known delay circuit includes a first inverter 21 and a second inverter 22 connected to an output of the first inverter 21. The first inverter 21 is arranged to have a p-type MOS transistor 23 and an n-type MOS transistor 24, the drains of which are connected to each other. The input of the delay circuit is fed to the gates of the p-type MOS transistor 23 and the n-type MOS transistor 24. The contact of the drains serves as an output of the inverter 21.
The second inverter 22 is, likewise, arranged to have a p-type MOS transistor 25 and an n-type MOS transistor 26, the drains of which are connected to each other. The output of the first inverter 21 is fed to the gates of the p-type MOS transistor 25 and the n-type MOS transistor 26. The contact of the drains serves as an output of the delay circuit.
The output of the first inverter 21 is connected to a p-type MOS capacitor 27 and an n-type MOS capacitor 28. That is, at the output of the first inverter 21, there exists as capacitance the p-type MOS capacitor 27, the n-type MOS capacitor 28, and the gate capacitances of the p-type MOS transistor 25 and the n-type MOS transistor 26 composing the second inverter 22.
When the input of the inverter 21 instantly changes from low (GND) level to high (Vcc) level, the p-type MOS transistor 23 is turned off and the n-type MOS transistor 24 is turned on, so that the output of the inverter 21 which has high-level may be connected to the ground (GND) through the effect of the on resistance of the n-type MOS transistor 24. That is, the output voltage of the inverter 21 gradually lowers through the effect of the capacitor and the on resistance. If it becomes lower than the inverted voltage of the inverter 22, the output of the inverter 22 changes from low level to high level. The resulting delay time is about 0.7 Rn C, in which Rn denotes an on resistance of the n-type MOS transistor 24, C denotes all the capacitance of the capacitors, and the inverted voltage of the inverter 22 is 1/2 Vcc. When the input of the inverter 21 changes from high level to low level, the similar delay may take place. The delay time is about 0.7 Rp C, in which Rp denotes an on resistance of the p-type MOS transistor 23.
In the known pulse delay circuit, however, some essential parameters for defining a delay time are variable due to some factors such as a manufacturing variety, a device temperature, and a supply voltage. The known pulse delay circuit, therefore, cannot to provide an accurate delay time. Further, the use of such a pulse delay circuit makes it quite difficult to generate phases accurately delayed by a predetermined period.
Further, the clock generator provided in a microprocessor needs to receive a high frequency clock. The frequency of the necessary clock is integer times as high as that of the output clock, because the clock generator has to generate two or more phases. This leads to an obstacle to speeding up the clock generator and a loss of power consumption.